Semiconductor storing device

ABSTRACT

A semiconductor storing device can access a plurality of addresses simultaneously without increasing a circuit area and a wiring area. A row of memory cells is selected by two stages of a word line and a division word line. An address is specified by X[i:0], Y[j:0], and Z[k:0]. Two roots of selection signals are alternately provided to division word line selectors arranged in one memory array. One of two roots of the selection signals is enabled to select the division word line selector. Eight roots of the selection signals in the entire semiconductor storing device are enabled to access eight addresses simultaneously.

TECHNICAL FIELD

The present invention relates to a semiconductor storing device, andspecifically relates to a semiconductor storing device that can access aplurality of addresses simultaneously.

BACKGROUND ART

A digital image output apparatus such as a digital color copier reads animage as data of R (red), G (green), and B (blue) via a reading unit ofthis apparatus. The digital image output apparatus outputs this data asthe data of C (cyan), M (magenta), and Y (yellow) to a printing unit ofthis apparatus. Accordingly, in the image processing of the digitalimage output apparatus, coordinate conversion from a RGB color space toa CMY color space is performed on the image data. In this coordinateconversion process, it is necessary to take into account an inputproperty of a scanner and an output property of a plotter, and convertedcoordinate values cannot be calculated in a simple manner.Conventionally, a three-dimensional lookup table (hereinbelow, referredto as LUT) is used. However, depending on a bit width of RGB data, alarge capacity can be required to configure the LUT. For example, when Rdata, G data, and B data is represented by the widths of 8 bits,respectively, the bits of 2⁸×2⁸×2⁸ are required for the capacity of theLUT.

Conventionally, in order to reduce the capacity of the LUT, the colorconversion process is performed as follows. A conventional configurationof a color conversion processing unit 90 is schematically shown in FIG.15. This color conversion processing unit 90 includes a color conversiondata memory area 91, and a correcting operation unit 92. C data, M data,and Y data that is formed by the upper 4 bits of R is written asaddresses in the color conversion memory region in advance. C data, Mdata, and Y data that is formed by the upper 4 bits of G is written asaddresses in the color conversion memory region in advance. C data, Mdata, and Y data that is formed by the upper 4 bits of B is written asaddresses in the color conversion data memory area 91 in advance. Asshown in FIG. 15, the three color conversion processing units 90 areprepared for the conversion to C data, the conversion to M data, and theconversion to Y data, respectively. Accordingly, the three colorconversion data memory areas 91 in the respective color conversionprocessing units 90 correspond to the respective LUTs for the conversionto C data, the conversion to M data, and the conversion to Y data,respectively.

The upper 4-bit R data, the upper 4-bit G data, and the upper 4-bit Bdata out of the binary digit data of 8 bits read by a scanner (notshown) are used to read the data by using color conversion data memoryareas 91. That is, at this time, one of the read data corresponds to abase address specified by the upper 4-bit data of R, G, and B, and theothers of the read data correspond to predetermined addresses that areselected based on the base address. FIG. 16 shows one example of aplurality of addresses that are selected based on the base address (z,y, x) and are used for the data reading process.

When accessing a cyan memory area based on the base address (z, y, x)that is specified by the upper 4-bit data of R, G, and B, the baseaddress indicated by “0” of FIG. 16 is selected, and a plurality ofaddresses (indicated by {circle around (1)} through {circle around (7)}of FIG. 16 that are determined by adding “1” to one, two, and all of x,y, and z constituting the base address are selected. In other words, 8addresses including the base address (z, y, x) that define one cube, forexample, are selected, as shown in FIG. 16. The data that corresponds tothe selected plural addresses is read from the cyan memory area. Thisread data is rough information because the read data is based on theupper 4-bit data of R data, G data, and B data.

Thereafter, in order to obtain fine information, the lower 4-bit data ofR data, G data, and B data is used. The correcting operation unit 92performs a correcting arithmetic operation by using the data. In thismanner, the fine information about the cyan data that is included in thecube of FIG. 16 defined by the eight addresses can be obtained, and thedata on which the color conversion is performed can be extracted.

In the same manner of obtaining the cyan data, the color conversionprocessing units 90 perform the color conversion process so as to obtainM data and Y data. The data corresponding to eight addresses isgenerally used, but the data corresponding to six addresses is also usedin this field.

Generally, the above-described color conversion data memory area isformed by a plurality of RAMs. One example of the conventional RAM isshown in FIG. 17. In this example, the RAM is a static RAM, and a memorycell is selected by two stages, that is, by a word line and a divisionword line.

The RAM 100 includes a plurality of memory arrays 101 (1^(st) blockthrough a^(th) block) having the same cell configuration. In each of thememory arrays 101, “c” number of word lines WL are respectivelyconnected to division word lines DWL via division word line selectors102. Memory cells whose number is “b” are connected to each of thedivision word lines DWL. Each of the memory cells 103 (MC) correspondsto one bit. At each column, the memory cells 103 are connected to a pairof bit lines BL and BLB so as to be located between the pair of bitlines BL and BLB. One end of each of the bit lines BL and BLB areconnected to a pre-charging circuit 104. The bit lines BL and BLB areconnected to a pair of data lines DL and DLB via a column gate 105. Eachpair of data lines DL and DLB are connected to a data input/outputcircuit 108 via a sense operational amplifier 106 and a write buffer107.

In the RAM 100, data is read from the memory cells 103 of each memoryarray 101, and data is written in the memory cells 103 of each memoryarray 101. This reading/writing operation is performed based on anaddress signal and a control signal that are sent to a row decoder 109and a column decoder 110 from an address input circuit 111 and aninternal control circuit 112. In other words, the address input circuit111 and the internal control circuit 112 send the address signal and thecontrol signal to the row decoder 109 and the column decoder 110 basedon an external signals indicated by CEB, WEB, and ADD[h:0] in FIG. 17.The opening/closing of column gates 105 is controlled by selectionsignals G[a-1:0] output from the column decoder 110. At the time of theoperation, the selection signals G[0] through G[a-1] as gate signals areone-by-one input to the 1^(st) memory array through the a^(th) memoryarray, respectively. One of the “a” number of the gate signals is madeto rise so that only one of the “a” number of the memory arrays can beselected.

One division word line DWL to which “b” number of memory cells 103 areconnected forms one word in each memory array 101. Accordingly, the RAMhaving such a configuration has a capacity of: a×c(words)×b(bits).

In FIG. 17, ADD[h:0] is shown as an input terminal of the address inputcircuit 111 (“h” is equal to or larger than “2”). However, three typesof addresses X[i:0], Y[j:0], and Z[k:0] may be used as address inputterminals. In this case, the address X is decoded by the row decoder109, and the addresses Y and Z are decoded by the column decoder 110.

When all of “i”, “j”, and “k” are “1”, “c” is “4”, and “a” is “16”. FIG.18A shows one example of the address arrangement of the RAM having thestoring area of “a×c” words. This RAM has respective blocks each ofwhich forms one word. As shown in FIG. 18B, one block 115 correspondingto one word is configured so as to include one word line selector 102and the division word line DWL having the “b” number of memory cellsconnected to this division word line DWL.

The addresses input from the address input terminals X[i:0], Y[j:0], andZ[k:0] are expressed by (z, y, x). In the case of simultaneously usingthe data corresponding to eight addresses that are made by adding “1” toone, two, and all of “x”, “y”, and “z” and that includes the baseaddress (z, y, x) (refer to FIG. 16), the data corresponding to eightblocks indicated by “0” through “{circle around (7)}” of FIG. 18A issimultaneously required. In this example, (z, y, x)=(00, 00, 01)indicates Z[1]=Z[0]=0, Y[1]=Y[0]=0, and X[1]=X[0]=1.

However, in the case of the RAM having the configuration shown in FIG.17, the eight specified addresses correspond to blocks that are adjacentto each other, as shown in FIG. 18A. Furthermore, in this case, eachpair of bit lines BL and BLB is shared by the blocks. Accordingly, thedata corresponding to the eight addresses cannot be read simultaneouslyby one cycle. As one example, in order to simultaneously use the datacorresponding to the eight addresses, eight RAMs are used, at the timeof writing, the same data is written in the same address of each of theeight RAMs, and at the time of reading, data is output from therespective different addresses of the respective RAMs, for example.However, in this case, the entire chip area becomes large.

As another example, in order to use the data corresponding to the eightaddresses, eight other RAMs each of which has one eighth of capacity ofthe RAM shown in FIG. 18A, i.e., has the capacity of a×c=4×2, are used.In FIG. 19A, the blocks 115 of FIG. 18A that are specified by the Xaddress, the Y address, and Z address are respectively distributed tothe eight RAMs each of which has a capacity of a×c=4×2. That is, by thisaddress distribution, the blocks 115 of the eight addresses that areaccessed simultaneously are distributed to the eight RAMs, respectively.In this example, “0” to “{circle around (7)}” shown in FIG. 19Acorrespond to “0” to “{circle around (7)}” shown in FIG. 18A. In orderto simultaneously access the eight addresses of the eight RAMs such as“0” to “{circle around (7)}” shown in FIG. 19A, a peripheral circuitexternal to the eight RAMs may decode the addresses, as shown in FIG.19B.

With this configuration, it is possible to simultaneously use the datacorresponding to the eight addresses without changing the total RAMcapacity. However, in this case, the RAM is divided into eight blockgroups, so that each block group needs a specific control circuit. As aresult, plural control circuits are used. In addition, a wiring area forthe connection between the eight block groups and an external addressdecoder is required, so that the entire area becomes large.

Furthermore, in order to simultaneously access the eight addresses,“8×b” number of wires for transmitting and receiving data are requiredfor the only input use, and this number of the wires for transmittingand receiving data increases by two times when taking into account theoutput use. Accordingly, the entire area becomes large.

In order to simultaneously access eight addresses, Japanese Laid-OpenPatent Application No. 6-349268 discloses a semiconductor storing devicethat can perform one writing operation to simultaneously write data in aplurality of consecutive memory cells that belong to one row address andthat are in an arbitrary range. Further, Japanese Laid-Open PatentApplication No. 5-113928 discloses an image memory apparatus thatconverts an address, and can simultaneously access a plurality of memorycells either in the case of data of plural kinds of displaying elementscorresponding to the same pixel or in the case of data of the same kindof displaying elements corresponding to plural pixels.

In these two prior techniques, it is possible to simultaneously access aplurality of addresses. However, the simultaneous access to a pluralityof addresses is limited to one row address. Objects of these priortechniques are different from the object of the present invention whichis to simultaneously access a plurality of addresses that are selectedbased on the base address (z, y, x).

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a semiconductorstoring device that enables a plurality of addresses to be accessedsimultaneously without increasing a circuit area and a wiring area.

According to one aspect of the present invention, there is provided asemiconductor storing device in which a row of memory cells is selectedby a word line stage and a division word line stage, comprising:

memory arrays that each include a plurality of memory cells arranged ina matrix;

word lines for respective rows of the memory cells;

division word lines each of which is connected to the memory cellsarranged in one row corresponding to one word;

division word line selectors that select the division word lines,respectively, the division word lines being connected to the respectiveword lines via the division word line selectors, respectively;

pairs of bit lines for reading data from the memory cells and writingdata to the memory cells that are connected to the pairs of the bitlines, respectively;

column gates connected to the pairs of bit lines, respectively;

pairs of data lines that are connected to the pairs of bit lines via thecolumn gates, respectively, to communicate data;

write buffers for data writing that are connected to the pairs of datalines, respectively;

sense operational amplifiers for data reading that are connected to thepairs of data lines, respectively; and

data input/output circuits that are connected to the pairs of data linesvia the write buffers and the sense operational amplifiers,respectively,

wherein input address data is specified by address data X[i:0], Y[j:0],and Z[k:0], two roots of selection signals for selecting the divisionword line selectors are provided alternately to the division word linesarranged in one of the memory arrays, and one of the two roots of theselection signals is enabled to select one of the division word lineselectors in the one of the memory arrays, and

eight roots of the selection signals in the entire semiconductor storingdevice are enabled so that when an address (z, y, x) is specified by theinput address data X[i:0], Y[j:0], and Z[k:0], eight addresses of (z, y,x), (z, y, x+1), (z, y+1, x), (z, y+1, x+1), (z+1, y, x), (z+1, y, x+1),(z+1, y+1, x), and (z+1, y+1, x+1) are accessed simultaneously.

Four roots of selection signals for selecting the division word lineselectors may be provided to the division word lines arranged in one ofthe memory arrays, and one of the four roots of the selection signalsmay be enabled to select one of the division word line selectors in theone of the memory arrays.

With this semiconductor storing device, it is possible to simultaneouslyaccess eight addresses in one RAM, and to decrease a circuit area and awiring area compared with the conventional configuration.

According to another aspect of the present invention, four roots of theselection signals in the entire semiconductor storing device may beenabled so that when an address (z, y, x) is specified by the inputaddress data X[i:0], Y[j:0], and Z[k:0], four addresses of (z, y, x),(z, y, x+1), (z, y+1, x), and (z, y+1, x+1) may be accessedsimultaneously.

With this semiconductor storing device, it is possible to simultaneouslyaccess four addresses in one RAM, and to decrease a circuit area and awiring area compared with the conventional configuration.

According to another aspect of the present invention, the semiconductorstoring device further comprises selectors that are provided between thewrite buffers and the data input/output circuits, and between the senseoperational amplifiers and the data input/output circuits, respectivelysuch that the data input/output circuits always correspond one-to-one tothe eight addresses of (z, y, x), (z, y, x+1), (z, y+1, x), (z, y+1,x+1), (z+1, y, x), (z+1, y, x+1), (z+1, y+1, x), and (z+1, y+1, x+1),respectively, and always transmit and receive, via the selectors,respective input data and output data corresponding one-to-one to theeight addresses, respectively.

With this semiconductor storing device, data input and data outputcorresponding to respective eight addresses that are determined based onthe address (z, y, x) are assigned to respective data input/outputcircuits, so that it is not necessary to provide an additional externalcircuit, and an outside wiring area can be decreased.

According to another aspect of the present invention, when at least oneof z, y, and x of the address (z, y, x) is an allowable maximum value,at least one of z+1, y+1, and x+1 that corresponds to the at least oneof x, y, and z having the allowable maximum value is converted to “0” toaccess the eight addresses simultaneously.

With this semiconductor storing device, it is possible to decrease acircuit area and a wiring area.

According to another aspect of the present invention, the semiconductorstoring device further comprises selection means for selecting either afirst mode in which the eight addresses are accessed simultaneously, ora second mode in which a single address is accessed.

With this semiconductor storing device, when only one address isrewritten, it is not necessary to prepare the same data as the dataalready written in the other addresses in order to prevent the data ofthe other addresses from being changed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a RAM configuration according to a firstembodiment of the present invention.

FIG. 2 shows address arrangement for memory arrays of a×c=16×4 whereaddress value “00” is converted to “0”, the address value “01” isconverted to “1”, the address value “10” is converted to “2”, and theaddress value “11” is converted to “3” to express the address (z, y, x)that is determined by X[1:0], Y[1:0], and Z[1:0].

FIG. 3A shows one example of address arrangement according to the firstembodiment where one address is selected for every two lateral blocks.

FIG. 3B shows the address arrangement of FIG. 3A by another expression.

FIG. 4A shows access positions in the address arrangement of FIG. 3Awhen a base address (z, y, x) is (0, 0, 0).

FIG. 4B shows access positions in the address arrangement of FIG. 3Awhen a base address (z, y, x) is (1, 1, 0).

FIG. 4C shows access positions in the address arrangement of FIG. 3Awhen a base address (z, y, x) is (2, 2, 1).

FIG. 4D shows access positions in the address arrangement of FIG. 3Awhen a base address (z, y, x) is (1, 1, 1).

FIG. 5 shows an internal configuration of a column decoder.

FIG. 6 shows an internal configuration of a row decoder.

FIG. 7 shows address arrangement related to a conventional RAM.

FIG. 8 shows one example of address arrangement for the RAM of FIG. 1.

FIG. 9 shows the address arrangement of FIG. 8 by another expression.

FIG. 10 shows a part of a RAM according to a second embodiment of thepresent invention.

FIG. 11 shows a part of a RAM having a selection signal line of thethird embodiment.

FIG. 12 shows an example of a configuration of a row decoder of thethird embodiment.

FIG. 13 shows an example of a configuration of a column decoder of thethird embodiment.

FIG. 14A shows an example of address arrangement according to a sixthembodiment of the present invention.

FIG. 14B shows the address arrangement of FIG. 14A by anotherexpression.

FIG. 15 shows a color conversion data memory area including a pluralityof memory arrays in the related art.

FIG. 16 is an illustration for address selection in which a plurality ofaddresses for data accessing are selected based on a base address.

FIG. 17 shows a RAM in the related art.

FIG. 18A shows an example of address arrangement of memory arrays havinga memory area of (a×c) words in the related art.

FIG. 18B shows one block corresponding to “b” bits in the memory arraysof FIG. 18A.

FIG. 19A shows an example of address arrangement in a RAM includingeight regions each of which has an area of (a×c=4×2) in the related art.

FIG. 19B schematically shows a circuit configuration of the RAM shown inFIG. 19A.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described with reference tothe drawings.

FIG. 1 is a block diagram schematically showing a RAM 10 according to afirst embodiment of the present invention. The RAM 10 includes aplurality of memory arrays 1 (corresponding to 1^(st) block througha^(th) block) having the same cell configuration. In each memory array1, the “c” number of word lines WL are connected to division word linesDWL, respectively via division word line selectors 2. The “b” number ofmemory cells 3 (MC) that form one word are connected to each of thedivision word lines DWL. At each column address, the memory cells 3 areconnected to a pair of bit lines BL and BLB so as to be located betweenthe bit lines BL and BLB. One ends of the bit lines BL and BLB areconnected to a pre-charging circuit 4.

Respective pairs of the bit lines BL and BLB are connected viarespective column gates 5 to respective pairs of data lines DL and DLB.1^(st) through 8^(th) data line sets 8 having these pairs of data linesare arranged as shown in FIG. 1. Each pair of the data lines DL and DLBis connected via a sense operational amplifier 9 and a write buffer 11to a data input/output circuit 12.

In the RAM 10, in accordance with an external signal, an address signaland a control signal for the memory cells 3 of each memory array 1 aresent from an address input circuit 14 and an internal control circuit 13to a row decoder 7 and a column decoder 6. In this manner, variousoperations such as data reading from the memory cell 3 in each memoryarray 1 and the data writing to the memory cell 3 in each memory array 1are controlled based on the address signal and the control signal.

In this example, three types of address data. i.e., address dataX[[1:0], Y[1:0], and Z[1:0] (also referred to as X, Y, and Z) is inputto input terminals of the address input circuit 14, the row decoder 7decodes the address data X and the address data Y, and the columndecoder 6 decodes the address data X and the address data Z.

As in the address arrangement of FIG. 18A, FIG. 2 shows the addressarrangement in the case of X[1:0], Y[1:0], and Z[1:0]. In this addressarrangement of FIG. 2, the address value “00” is converted to “0” theaddress value “01” is converted to “1”, the address value “10” isconverted to “2”, and the address value “11” is converted to “3”. InFIG. 2, the blocks on which the oblique lines rising at the left sideare drawn correspond to the eight addresses that are selected based onthe base address (z, y, x)=(1, 1, 1) in the same manner shown in FIG.16. In order to simultaneously read data from these eight addresses, itis necessary to access the eight addresses of the blocks on which theoblique lines are drawn.

In order to achieve the object of the present invention, the memorycells 3 belonging to the eight selected addresses on which the readingoperation is simultaneously performed should not share the pair of thebit lines BL and BLB. For this reason, the address arrangement of FIG. 2is changed to the address arrangement of FIG. 3A, for example. There areseveral patterns for distributing the addresses, but in the addressarrangement shown in FIG. 3A, one address is selected from every twoblocks with respect to the lateral direction of FIG. 3A. As in theexample of FIG. 2, the blocks of FIG. 3A on which the oblique linesrising at the left side are drawn correspond to the eight addresses thatare selected based on the cube shown in FIG. 16. In FIG. 3B, the sameaddress arrangement as that of FIG. 3A is shown in another manner.

In FIGS. 4A through 4D, examples of the distribution of the eightselected address are shown in the case of the base addresses of thesefigures that are different from each other. FIGS. 4A, 4B, 4C, and 4Dcorrespond to the base address (z, y, x)=(0, 0, 0), (1, 1, 0), (2, 2,1), and (1, 1, 1), respectively. In each of FIGS. 4A through 4D, 0through {circle around (7)} correspond to 0 through {circle around (7)}shown in FIGS. 16 and 18A. As understood from FIGS. 4A through 4D, thepositions of accessed addresses are roughly classified into two types.

In FIGS. 4A and 4B, at each of the right and left sides of the rowdecoder, the addresses that are accessed are arranged in the same row,so that one word line WL needs to rise at each of the right and leftsides of the row decoder. On the other hand, in FIGS. 4C and 4D, at eachof the right and left sides of the row decoder, the addresses that areaccessed are arranged in different rows. To be specific, in FIG. 4C, ateach of the right and left sides of the row decoder, the addresses arearranged in two upper rows. In FIG. 4D, at the left side of the rowdecoder, the addresses are arranged in two upper rows, and at the rightside of the row decoder in FIG. 4D, the addresses are arranged in twolower rows. In the case of FIGS. 4C and 4D, two word lines WL need torise at each of the right and left sides of the row decoder.

In the case of the conventional RAM as shown in FIG. 17, when two wordlines WL that are located at the same side of the row decoder risesimultaneously, and the selection signals G[a-1:0] of the division wordlines 102 are enabled, the two division word lines DWL are made to risesimultaneously in one memory array 101. Accordingly, there is a problemin that the data collides with each other via the pair of the bit linesBL and BLB. In order to solve this problem, according to the firstembodiment of the present invention, as shown in FIG. 1, two types ofroots GA and GB regarding selection signals GA[a-1:0] and GB[a-1:0] forthe division word line selectors 2 are used, and are alternatelyconnected row by row to the division word line selectors 2 arranged inthe longitudinal direction. With this configuration, at each memoryarray 1, one of the roots GA and GB regarding the selection signalsGA[a-1:0] and GB[a-1:0] is made to rise, or neither of the roots GA andGB regarding the selection signals GA[a-1:0] and GB[a-1:0] is made torise. In this manner, it is possible to avoid the collision of the dataeven if the two word lines WL are simultaneously made to rise at oneside of the row decoder.

In the case of the RAM 10 shown in FIG. 1, the eight sets of the datalines DL and DLB are arranged. This arrangement of the data lines DL andDLB is applied to the address arrangement where one address is selectedfrom the blocks arranged in the lateral direction, as shown in FIG. 3A.In this example, the memory cells 3 positioned at the respective “b”number of columns are connected to each division word line DWL, and ifa=16, the memory cells 3 corresponding to the two blocks are connectedto each set of the data lines DL and DLB. Furthermore, the senseoperational amplifiers 9 and the write buffers 11 corresponding to the“b” bits are also connected to each set of the data lines DL and DLB.

When either GA or GB regarding the selection signal GA[a-1:0] and theselection signal GB[a-1:0] output from the column decoder 6 is made tobe enabled, the column gate 5 releases a gate between the pair of thebit lines BL and BLB and the pair of the data lines DL and DLB. Whenboth the selection signal GA[a-1:0] and the selection signal GB[a-1:0]are disabled, the pre-charging circuit 4 pre-charges the pair of the bitlines BL and BLB. In one memory array 1, the column decoder 6 causes thetype GA regarding the selection signal roots GA[a-1:0] or the type GBregarding the selection signal roots GB[a-1:0] to be enabled inaccordance with the address values (z, y, x). The enabled selectionsignal roots (i.e., selection signals) out of GA[a-1:0] and GB[a-1:0]are input to the blocks including the eight accessed addresses that areselected out of the 1^(st) through a^(th) blocks. The row decoder 7causes one word line WL at each side of the row decoder 7 or two wordlines WL at each side of the row decoder 7 to rise in accordance withthe address values (z, y, x).

In the first embodiment, the row decoder 7 is positioned at the centerpart of the RAM 10. That is, each side of the row decoder 7 has the samenumber of the memory arrays 1. In this example, if all of the memoryarrays 1 are arranged at one side of the row decoder 7, the four wordlines WL at most need to rise, and only the selection signal types ofroots GA and GB regarding the selection signal roots GA[a-1:0] and theselection signal roots GB[a-1:0] do not avoid the data collision on thebit lines. In order to avoid this data collision, the row decoder 7 ispositioned at the center part of the RAM 10, as shown in FIG. 1. If thecolumn decoder 6 is connected to each of the all memory arrays 1 of FIG.1, the row decoder 7 needs not to be positioned at the center part ofthe RAM 10.

An example of a circuit configuration of the column decoder 6 for theaddress arrangement of FIG. 3A is shown in FIG. 5, and an example of acircuit configuration of the row decoder 7 for the address arrangementof FIG. 3A is shown in FIG. 6. In this example, it is assumed that “a”is “16”, and “c” is “4”. In these circuit configurations, the addressinputs X[1:0] and Y[1:0] are decoded by the column decoder 6, and theaddress input Z[1:0] is decoded by the row decoder 7.

In FIGS. 3A and 3B, and 4A through 4D, the values of z, y, and x of thebase address (z, y, x) are equal to or smaller than “2”. In the exampleof FIGS. 7 through 9, one of z, y, and x of the base address (z, y, x)is “3”. An example of the address arrangement of from (0, 0, 0) to (4,4, 4) is shown in FIG. 7 (FIG. 7 shows the address arrangement relatedto the conventional RAM 100 of FIG. 17). In this case, three inputaddress data X[2:0], three input address data Y[2:0], and three inputaddress data Z[2:0] is required, and address value conversion isperformed such that “000” is converted to “0”, “001” is converted to“1”, “010” is converted to “2”, “011” is converted to “3”, and “100” isconverted to “4”, in order to express the address by (z, y, x). In FIG.7, the blocks on which the oblique lines rising at the left side aredrawn correspond to the eight addresses that are selected based on thebase address (z, y, x)=(3, 3, 3) in the manner shown in FIG. 16.

Similar to the case of FIG. 18A, in the case of FIG. 7, each group ofthe four selected addresses correspond to the blocks that are adjacentto each other. Every two blocks at the same column share the pair of thebit lines BL and BLB, so that the data corresponding to the eightaddresses cannot be read during one cycle.

FIG. 8 (related to the first embodiment of the present invention) showsan alternative example of the address arrangement of FIG. 7. In FIG. 8,the blocks on which the oblique lines rising at the left side are drawncorrespond to the eight addresses that are selected based on the baseaddress (z, y, x)=(3, 3, 3) in the same manner of FIG. 16. In thisexample of FIG. 8, “a” of FIG. 1 is “24”, and “c” of FIG. 1 is “9”.Furthermore, as shown in FIG. 8, three blocks including division wordlines arranged in one memory array 1 are connected to each data line set8. In order to form the address arrangement that enable plural addressesto be accessed simultaneously, this address arrangement needs to includeblocks (indicated by the oblique lines rising at the right side)corresponding to the address value of “5” that is not necessary. Theaddress value of “5” is the value converted from the address “101” of X,Y, or Z. In practical use, the addresses having the address value of “5”are not accessed, and the columns where the address value z is 5 can beomitted from the layout.

The address arrangement of FIG. 8 is shown in FIG. 9 by anotherexpression. As described above, the address arrangement of FIG. 7 needsthree input address data X[2:0], three input address data Y[2:0], andthree input address data Z[2:0]. On the other hand, in the addressarrangement of FIGS. 8 and 9, when the base address (z, y, x) (i.e., theaddress corresponding to “0” of FIG. 16) has the address values rangingfrom (0, 0, 0) to (3, 3, 3), it is possible to access the addressescorresponding to the required address values ranging from (0, 0, 0) to(4, 4, 4). Therefore, in the example of FIGS. 8 and 9, two input addressdata X[1:0], two input address data Y[1:0], and two input address dataZ[1:0] suffice.

The area of the address arrangement shown in FIG. 8 is larger than thearea of the address arrangement shown in FIG. 7. However, in the case ofusing eight RAMs (memory arrays) each of which has a part of the entirecapacity, the address arrangement of FIG. 7 cannot be divided into eightparts each having the same capacity as described above by referring toFIGS. 19A and 19B, and the RAM (memory array) having one eighth of thisentire capacity of FIG. 7 is not available. For this reason, it isnecessary to use RAMs (memory arrays) that each have a capacity largerthan one eighth of the entire capacity. Furthermore, when a wiring areais taken into account, the entire area required for the addressarrangement shown in FIG. 8 becomes smaller than the entire arearequired for the address arrangement shown in FIG. 7. Accordingly, theaddress arrangement of FIG. 8 is more advantageous in terms of theentire area.

According to the RAM of the first embodiment having the above-describedconfiguration, it is possible to access eight addresses simultaneously,that is, it is possible to read data from or write data to the eightaddresses simultaneously. When this RAM is actually configured, thecircuit area and the wiring area of this RAM is not increased.

Other embodiments of the present invention will be described, and in thefollowing, the same reference numbers of the first embodiment areattached to the same parts as those of the first embodiment

Next, a second embodiment of the present invention will be described.The blocks to which eight addresses determined based on the cube of FIG.16 are assigned change, depending on the base address values (z, y, x).This change of the assigned blocks can be seen from the difference inthe selected blocks of FIGS. 4A through 4D as indicated by “0” through“{circle around (7)}” of FIGS. 4A through 4D. In the configuration ofthe RAM 10 shown in FIG. 1, data corresponding to the address (z, y, x)is input to or output from predetermined “b”-bit data input/outputcircuits 12 (for example, positioned at the lower and most left part ofFIG. 1), the data corresponding to the address (z, y, x+1) is input toor output from the same predetermined “b”-bit data input/output circuits12 on another occasion, and other data corresponding to the otheraddresses is input to or output from the same predetermined “b”-bit datainput/output circuits 12 on other occasions, in accordance with thevalues of the base address (z, y, x). However, in this condition, usingthis RAM 10 is not convenient.

According to the second embodiment of the present invention, eight setsof buses DLSET_(—)DIO are arranged between the sense operationalamplifier 9/the write buffer 11 and the data input/output circuit 10 asshown in FIG. 10 in order to solve this inconvenience. Each set of busesDLSET_(—)DIO includes “b” number of signal lines. Further, a selector 19is arranged between each data input/output circuit 12 and the busesDLSET_(—)DIO. Based on the input from the address input circuit 12, theselector 19 selects the data corresponding to a predetermined address,and allows the selected data to pass the selector 19. With thisconfiguration, the data corresponding to the address (z, y, x) is alwaysinput to or output from a certain group corresponding to the “b” numberof the data input/output circuits 12, and the data corresponding to theaddress (z, y, x+1) is always input to or output from another group ofthe “b” number of the data input/output circuits 12. As for other groupsof the “b” number of the data input/output circuits 12, the datacorresponding to a predetermined address is input to or output from apredetermined group of the “b” number of the data input/output circuits12.

Next, a third embodiment of the present invention will be described.When it becomes necessary to rewrite the data of a single address in theRAM shown in FIG. 1 in which the data of the eight addresses can be readand written simultaneously, it is necessary to always prepare the datacorresponding to the eight addresses, input the data for rewriting inthis single rewriting address, and to input the data for the other sevenaddresses that each corresponds to the data already written in the otherseven addresses, in order to prevent the data already written in theother seven addresses from being changed. In order to solve thistrouble, according to the third embodiment of the present invention,there is provided a selection terminal that enables the operation modeto be selected from a first operation mode for simultaneously reading orwriting the data of eight addresses and a second mode for reading orwriting the data of a single address.

FIG. 11 shows a configuration where the selection terminal SEL is addedto the configuration shown in FIG. 1, according to the third embodimentof the present invention. For simplicity, only the internal controlcircuit 13, the address input circuit 14, the column decoder 26, and therow decoder 27 are shown in FIG. 11. The selection terminal SEL isconnected to the column decoder 26 and the row decoder 27. A selectionsignal provided from outside the RAM 10 is provided to the columndecoder 26 and the row decoder 27 via the selection terminal SEL.

FIG. 12 shows an internal configuration of the row decoder 27. In thisrow decoder 27, a first row decoder 37A for accessing eight addressescauses one or two signal lines out of signal lines MWL[c-1:0] to rise,and causes one or two signal lines out of signal lines MWL[c-1:0]′ torise. Meanwhile, a second row decoder 37B for accessing a single addresscauses a single signal line out of signal lines SWL[c-1:0] andSWL[c-1:0]′ to rise. The signal lines MWL[c-1:0], the signal linesMWL[c-1:0]′, the signal lines SWL[c-1:0], and the signal linesSWL[c-1:0]′ are connected to selectors 31, respectively. In thisexample, when SEL=0, signals at the side of the signal lines MWL[c-1:0]and MWL[c-1:0]′ are selected, and when SEL=1, a signal at the side ofthe signal lines SWL[c-1:0] and SWL[c-1:0]′ is selected.

FIG. 13 shows an internal configuration of the column decoder 26. Inthis column decoder 26, a third decoder 46A for accessing eightaddresses causes eight signal lines out of signal lines MGA[a-1:0] torise, and causes eight signal lines out of signal lines MGB[a-1:0] torise so as to access the blocks corresponding to the eight addresses.Meanwhile, a fourth decoder 46B for accessing a single address causes asingle signal line out of signal lines SG[a-1:0] to rise. The signallines MGA[a-1:0] and MGB[a-1:0] are connected to selectors 41,respectively. The signal lines SG[a-1:0] are connected to the selectors41 to which the signal lines GA[a-1:0] and GB[a-1:0] are connected suchthat the reference numbers inside the mark [ ] of SG[a-1:0] correspondto the same reference numbers of GA[a-1:0] and GB[a-1:0], as shown inFIG. 13. At the time of accessing a single address, a single word lineis made to rise, so that even if signal lines GA and GB having the samereference number inside the mark [ ] are made to rise, there is noproblem with this configuration. In this example, when SEL=0, signals atthe side of MGA and MGB are selected, and when SEL=1, a signal at theside of SG is selected.

As described above, in the third embodiment, the selection terminal SEL,and the column decoder 26 and the row decoder 27 are arranged in theabove-described manner, so that it is possible to select either thefirst mode where the eight addresses are accessed simultaneously or thesecond mode where a single address is accessed. Accordingly, dependingon operational necessity, it is possible to access a single addresswithout performing troublesome control.

In the third embodiment, at the time of accessing a single address inthe address arrangement shown in FIGS. 3A and 3B, two input address data(or two address input terminals) X[1:0], two input address data Y[1:0],and two input address data Z[1:0] suffices. On the other hand, in thecase of simultaneously accessing eight addresses in the addressarrangement shown in FIG. 8, when the base address values (z, y, x) arethe maximum values (3, 3, 3), it is possible to access up to the addressvalues (4, 4, 4) that are generated by adding “1” to each of the baseaddress values (3, 3, 3). However, in the address arrangement shown inFIG. 8, at the time of accessing a single address, it is necessary touse three input address data X[2:0], three input address data Y[2:0],and three input address data Z[2:0].

Next, a fourth embodiment of the present invention will be described. Inthe address arrangement shown in FIGS. 3A and 3B, there is no addresshaving the address value “4”. Accordingly, the base address having theaddress value “3” is not applied to the address arrangement shown inFIGS. 3A and 3B. In order to solve this problem, there is provided amethod for accessing the address having the address value of “0” insteadof accessing the address having the address value “4”. This accessmethod according to the fourth embodiment can be applied to the addressarrangement shown in FIGS. 3A and 3B by configuring a column decodershown in FIG. 5 and a row decoder shown in FIG. 6 so as to use the baseaddress (z, y, x) having the address value “3”.

Furthermore, in the fourth embodiment, as for the address arrangementshown in FIG. 8, when the maximum allowable base address value of (z, y,x) is “4”, the address value “5” that is generated by adding “1” to thebase address that includes the address value “4” is not used. In thiscase, instead of accessing the address having the address value “5”, theaddress having the address value “0” is accessed. That is, in the caseof the base address value “4” of z, y, x, “z+1” is converted to “0”,“y+1” is converted to “0”, and “z+1” is converted to “0”. This accessmethod according to the fourth embodiment can be applied to the addressarrangement shown in FIG. 8 by configuring a column decoder shown inFIG. 5 and a row decoder shown in FIG. 6 so as to use the base addressvalue “4” of z, y, x.

Next, a fifth embodiment of the present invention will be described. Inorder to realize a RAM that allows the data of eight addresses to beread and written simultaneously, the following another method can beused. In the case where four word lines WL at most are made to rise atone side of the row decoder 7 in the RAM 10 of the first embodiment, thedata collides with each other on the bit line BL. In order to solve thisproblem, according to the fifth embodiment, four roots of selectionsignals for the division word line selectors that are output from thecolumn decoder 6 are set for the division word line selectors arrangedin one memory array 1 such that the four roots of selection signals areseparately provided to four division word line selectors arranged in onememory array 1, respectively (this configuration is not shown in thedrawings). Furthermore, in the fifth embodiment, the RAM 10 may beconfigured such that one, two, or four word lines WL are made to risesimultaneously at each side of the row decoder. This configuration maycorrespond to the address arrangement of FIGS. 4A through 4D with therow decoder being omitted.

Next, a sixth embodiment of the present invention will be described.When high operation speed is not much required, a RAM that allows fouraddresses to be accessed simultaneously may be used instead of using theRAM that allows eight addresses to be accessed simultaneously. In thecase of the RAM that allows four addresses to be accessedsimultaneously, wiring for transmitting data becomes half of wiring ofthe RAM that allows eight addresses to be accessed simultaneously, andtherefore, a wiring area is decreased. As in FIG. 19A, one RAM ofc×a=2×8 is configured so as to comprise the RAMs including the marks “0”and “4”. In the same manner, another-RAM is configured so as to comprisethe RAM including “{circle around (1)}” and “{circle around (5)}”,another RAM is configured so as to comprise the RAM including “{circlearound (2)}” and “{circle around (6)}”, and another RAM is configured soas to comprise the RAM including “{circle around (3)}” and “{circlearound (7)}”. However, in this case where the four RAMs are used,control circuits inside the RAMs are overlapped, and a wiring area forconnecting the four RAMs to an external address decoding circuit becomesnecessary, resulting in an increased chip area.

On the other hand, according to the sixth embodiment of the presentinvention, there is provided a RAM that allows data of four addresses tobe read and written simultaneously in the same manner of the RAM thatallows data of eight addresses to be read and written simultaneously. Acircuit configuration of the RAM in the sixth embodiment is basicallythe same as that of the RAM shown in FIG. 1. However, the RAM of thesixth embodiment is different from the RAM shown in FIG. 1 in that thenumber of the signal lines that are enabled simultaneously for selectingthe division word lines is four instead of eight, and only four sets ofdata lines are provided in the sixth embodiment. For example, in thecase of the address arrangement shown in FIGS. 3A and 3B, when the baseaddress (z, y, x) is (1, 1, 1), the four word lines that include theaddresses (1, 1, 1), (1, 1, 2), (1, 2, 1), and (1, 2, 2) are made torise. In this case, a row decoder needs to be positioned at the centerpart of the RAM, or a row decoder needs to be provided to each of thememory arrays. Meanwhile, in the case of using the address arrangementshown in FIGS. 14A and 14B, two word lines WL at most need to risesimultaneously. Accordingly, in the case of using the addressarrangement of FIGS. 14A and 14B, if all of the memory arrays arearranged at one side of the row decoder, there is no problem.

Furthermore, by applying the circuit configuration of the secondembodiment to a circuit configuration of the sixth embodiment, the RAMthat allows four addresses to be accessed simultaneously can beconfigured so that the data corresponding to the address (z, y, x) isalways input to and output from a certain group of the “b” number ofdata input/output circuits, the data corresponding to the address (z, y,x+1) is always input to and output from another group of the “b” numberof data input/output circuits, and other data corresponding to otheraddresses is always input to and output from other groups of the “b”number of data input/output circuits, respectively.

In addition, in the same manner of the first mode and the second modedescribed in the third embodiment, it is possible to select either amode for accessing four addresses simultaneously or a mode for accessinga single address.

This patent application is based on Japanese priority patent applicationNo. 2002-060640 filed on Mar. 6, 2002, the entire contents of which arehereby incorporated by reference.

1. A semiconductor storing device in which a row of memory cells isselected by a word line stage and a division word line stage,comprising: memory arrays that each include a plurality of memory cellsarranged in a matrix; word lines for respective rows of the memorycells; division word lines each of which is connected to the memorycells arranged in one row corresponding to one word; division word lineselectors that select the division word lines, respectively, thedivision word lines being connected to the respective word lines via thedivision word line selectors, respectively; pairs of bit lines forreading data from the memory cells and writing data to the memory cellsthat are connected to the pairs of the bit lines, respectively; columngates connected to the pairs of bit lines, respectively; pairs of datalines that are connected to the pairs of bit lines via the column gates,respectively, to communicate data; write buffers for data writing thatare connected to the pairs of data lines, respectively; senseoperational amplifiers for data reading that are connected to the pairsof data lines, respectively; and data input/output circuits that areconnected to the pairs of data lines via the write buffers and the senseoperational amplifiers, respectively, wherein input address data isspecified by address data X[i:0], Y[j:0], and Z[k:0], two roots ofselection signals for selecting the division word line selectors areprovided alternately to the division word lines arranged in one of thememory arrays, and one of the two roots of the selection signals isenabled to select one of the division word line selectors in the one ofthe memory arrays, and eight roots of the selection signals in theentire semiconductor storing device are enabled so that when an address(z, y, x) is specified by the input address data X[i:0], Y[j:0], andZ[k:0], eight addresses of (z, y, x), (z, y, x+1), (z, y+1, x), (z, y+1,x+1), (z+1, y, x), (z+1, y, x+1), (z+1, y+1, x), and (z+1, y+1, x+1) areaccessed simultaneously.
 2. The semiconductor storing device accordingto claim 1, further comprising selectors that are provided between thewrite buffers and the data input/output circuits, and between the senseoperational amplifiers and the data input/output circuits, respectivelysuch that the data input/output circuits always correspond one-to-one tothe eight addresses of (z, y, x), (z, y, x+1), (z, y+1, x), (z, y+1,x+1), (z+1, y, x), (z+1, y, x+1), (z+1, y+1, x), and (z+1, y+1, x+1),respectively, and always transmit and receive, via the selectors,respective input data and output data corresponding one-to-one to theeight addresses, respectively.
 3. The semiconductor storing deviceaccording to claim 1, wherein when at least one of z, y, and x of theaddress (z, y, x) is an allowable maximum value, at least one of z+1,y+1, and x+1 that corresponds to the at least one of x, y, and z havingthe allowable maximum value is converted to “0” to access the eightaddresses simultaneously.
 4. The semiconductor storing device accordingto claim 1, further comprising selection means for selecting either afirst mode in which the eight addresses are accessed simultaneously, ora second mode in which a single address is accessed.
 5. A semiconductorstoring device in which a row of memory cells is selected by a word linestage and a division word line stage, comprising: memory arrays thateach include a plurality of memory cells arranged in a matrix; wordlines for respective rows of the memory cells; division word lines eachof which is connected to the memory cells arranged in one rowcorresponding to one word; division word line selectors that select thedivision word lines, respectively, the division word lines beingconnected to the respective word lines via the division word lineselectors, respectively; pairs of bit lines for reading data from thememory cells and writing data to the memory cells that are connected tothe pairs of the bit lines, respectively; column gates connected to thepairs of bit lines, respectively; pairs of data lines that are connectedto the pairs of bit lines via the column gates, respectively, tocommunicate data; write buffers for data writing that are connected tothe pairs of data lines, respectively; sense operational amplifiers fordata reading that are connected to the pairs of data lines,respectively; and data input/output circuits that are connected to thepairs of data lines via the write buffers and the sense operationalamplifiers, respectively, wherein input address data is specified byaddress data X[i:0], Y[j:0], and Z[k:0], four roots of selection signalsfor selecting the division word line selectors are provided to thedivision word lines arranged in one of the memory arrays, and one of thefour roots of the selection signals is enabled to select one of thedivision word line selectors in the one of the memory arrays, and eightroots of the selection signals in the entire semiconductor storingdevice are enabled so that when an address (z, y, x) is specified by theinput address data X[i:0], Y[j:0], and Z[k:0], eight addresses of (z, y,x), (z, y, x+1), (z, y+1, x), (z, y+1, x+1), (z+1, y, x), (z+1, y, x+1),(z+1, y+1, x), and (z+1, y+1, x+1) are accessed simultaneously.
 6. Thesemiconductor storing device according to claim 5, further comprisingselectors that are provided between the write buffers and the datainput/output circuits, and between the sense operational amplifiers andthe data input/output circuits, respectively such that the datainput/output circuits always correspond one-to-one to the eightaddresses of (z, y, x), (z, y, x+1), (z, y+1, x), (z, y+1, x+1), (z+1,y, x), (z+1, y, x+1), (z+1, y+1, x), and (z+1, y+1, x+1), respectively,and always transmit and receive, via the selectors, respective inputdata and output data corresponding one-to-one to the eight addresses,respectively.
 7. The semiconductor storing device according to claim 5,wherein in a case where when the address (z, y, x) is specified, anaddress determined by at least one of z+1, y+1, and x+1 does not existin the semiconductor storing device, the at least one of z+1, y+1, andx+1 is converted to “0” to access the eight addresses simultaneously. 8.The semiconductor storing device according to claim 5, furthercomprising selection means for selecting either a first mode in whichthe eight addresses are accessed simultaneously, or a second mode inwhich a single address is accessed.
 9. A semiconductor storing device inwhich a row of memory cells is selected by a word line stage and adivision word line stage, comprising: memory arrays that each include aplurality of memory cells arranged in a matrix; word lines forrespective rows of the memory cells; division word lines each of whichis connected to the memory cells arranged in one row corresponding toone word; division word line selectors that select the division wordlines, respectively, the division word lines being connected to therespective word lines via the division word line selectors,respectively; pairs of bit lines for reading data from the memory cellsand writing data to the memory cells that are connected to the pairs ofthe bit lines, respectively; column gates connected to the pairs of bitlines, respectively; pairs of data lines that are connected to the pairsof bit lines via the column gates, respectively, to communicate data;write buffers for data writing that are connected to the pairs of datalines, respectively; sense operational amplifiers for data reading thatare connected to the pairs of data lines, respectively; and datainput/output circuits that are connected to the pairs of data lines viathe write buffers and the sense operational amplifiers, respectively,wherein input address data is specified by address data X[i:0], Y[j:0],and Z[k:0], two roots of selection signals for selecting the divisionword line selectors are provided alternately to the division word linesarranged in one of the memory arrays, and one of the two roots of theselection signals is enabled to select one of the division word lineselectors in the one of the memory arrays, and four roots of theselection signals in the entire semiconductor storing device are enabledso that when an address (z, y, x) is specified by the input address dataX[i:0], Y[j:0], and Z[k:0], four addresses of (z, y, x), (z, y, x+1),(z, y+1, x), and (z, y+1, x+1) are accessed simultaneously.
 10. Thesemiconductor storing device according to claim 9, further comprisingselectors that are provided between the write buffers and the datainput/output circuits, and between the sense operational amplifiers andthe data input/output circuits, respectively such that the datainput/output circuits always correspond one-to-one to the four addressesof (z, y, x), (z, y, x+1), (z, y+1, x), and (z, y+1, x+1), respectively,and always transmit and receive, via the selectors, respective inputdata and output data corresponding one-to-one to the four addresses,respectively.
 11. The semiconductor storing device according to claim 9,wherein in a case where when the address (z, y, x) is specified, anaddress determined by at least one of z+1, y+1, and x+1 does not existin the semiconductor storing device, the at least one of z+1, y+1, andx+1 is converted to “0” to access the four addresses simultaneously. 12.The semiconductor storing device according to claim 9, furthercomprising selection means for selecting either a first mode in whichthe four addresses are accessed simultaneously, or a second mode inwhich a single address is accessed.